Search - udp fpga verilog

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[VHDL-FPGA-Verilog] Verilog_UDP DL : 0: 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-defined primitives. For example, we sometimes see the " primitive ... table ... endtable ... endendprimitive" This code segment can only be found in the book about interpretation. The online search, then they are always with the TCP/IP, UDP conflict. So, specifically to collect this stuff, hoping to help people solve the " user of the original language" related issues.
Date : 2025-07-01 Size : 123kb User : 龙也
[Other] UDP DL : 0: 用verilog实现的UDP协议，包括arp，udp，ip分段协议等，对于想用FPGA实现TCP/IP协议的人来说，应该会起到一定的帮助作用-Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc., who want to achieve TCP/IP protocol with the FPGA people, should play a helpful role
Date : 2025-07-01 Size : 17kb User : 王江
[VHDL-FPGA-Verilog] udp_send1 DL : 0: 基于FPGA的UDP硬件协议栈，全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。支持外部phy的配置，支持GMII和RGMII模式。以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data_valid, input gtx_clk, output logic tx_en-UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows: input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data
Date : 2025-07-01 Size : 52kb User : qiubin
[VHDL-FPGA-Verilog] udpip DL : 0: 赛灵思XILINX FPGA verilog写的UDP/IP协议，可用。-I am prepared to use verilog UDP protocol, the test is available.
Date : 2025-07-01 Size : 7kb User : 汪洋
[Embeded Linux] 用FPGA实现简单的UDPIP通信 DL : 0: 使用verilog语言实现了UDP协议网络通信(Verilog protocol is used to realize UDP protocol network communication)
Date : 2025-07-01 Size : 636kb User : 天地孤影i
[Internet-Network] CH03_RGMII_UDP_TEST DL : 0: 基于RGMII的UDP网络数据通信，学习FPGA的千兆以太网通信(RGMII based UDP network data communication, learning FPGA Gigabit Ethernet communications)
Date : 2025-07-01 Size : 5.79mb User : tian682018
[] UDP DL : 0: UPD 协议 fpga源代码 upd 接收 upd 发送 arp 协议解析(upd receive upd send arp protocol analysis)
Date : 2025-07-01 Size : 16kb User : TAOHONGYU
[VHDL-FPGA-Verilog] CH14_RGMII_UDP_TEST DL : 0: 用xilinx的SPARTAN6 实现的UDP，可通过PC机网络抓包工具进行发送和接收，增加了网络视频传输的接口，具有很好的参考价值(With the Xilinx implementation of the SPARTAN6 UDP, can be sent and received through PC network capture tools, increase the network video transmission interface, has a good reference value)
Date : 2025-07-01 Size : 6.79mb User : suifeg